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  SONETbloX™ - Altera Implementations

 

Example OC-48c 16-bit datapath implementation, using external CDR with integrated bit-to-byte alignment:
 


Configuration 1

Frame sync, descramble, B1 calculation, 1 second error accumulation:
230 LC + 0 RAM

Configuration 2
All of Configuration 1 with the following additions: B2 calculation and 1 second error accumulation:
400 LC + 2 RAM

Configuration 3
All of Configuration 2 with the following additions:B3 calculation, concatenated pointer processor, payload extraction and payload BER measurement with 1 second error accumulation:
720 LC + 2 RAM

Configuration 4
All of Configuration 3 with the following additions: concatenated transmit section, which includes: B1/B2/B3 calculation and insertion, fixed pointer, ability to insert any overhead bytes such as D/E/F bytes.
1100 LC + 7 RAM


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