Cryptographic Intellectual Property Cores
 
  AES Encryption - Altera Implementations

 
AES-002R
• 16-bit data path
• Utilizes 2 internal M4K RAM blocks
• Uses 630 Logic Cells
• 190 MHz Fmax in C6 speed grade Cyclone
• 230 clocks to expand key 480 clocks to encrypt

AES-003R
• 16-bit data path
• Utilizes 3 internal M4K RAM blocks
• Uses 390 Logic Cells
• 245 MHz Fmax in C6 speed grade Cyclone
• 170 clocks to expand key
• 170 clocks to encrypt 16 byte word

AES-010R
• 128-bit data path
• Utilizes 10 internal M4K RAM blocks
• Uses 906 Logic Cells
• 240+ MHz Fmax in C6 speed grade Cyclone
• 30 clocks to simultaneously expand key and encrypt

AES-100R
• 128-bit data path
• Utilizes 100 internal RAM blocks
• 270+ MHz Fmax in C5 speed grade Stratix
• 3 clocks to simultaneously expand key and encrypt
• 35+ Gbps equivalent serial encryption rate

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